I was interviewing with one company in Austin, TX and I was asked to design a circuit which would generate the Fibonacci Series. By definition, the Fibonacci Series of numbers are 0, 1, 1, 2, 3, 5, 8, 13, etc. By default, the first two numbers are 0, and 1 and the next number in the sequence is calculated by adding the previous two numbers. The circuit also needed to support an

Below is the block level diagram which contains two registers to hold the current number and the next number in the sequence. There is also control logic for the enable signal which when asserted, the output of the two flops are added together and then the result is stored in the next number register (on that same cycle the next number register shifts into the current number register). When the enable signal is low, the registers hold their previous value.

Below is the Verilog code:

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*enable*input signal, which would control if the circuit should advance and calculate the next number in the sequence , or hold its previous value.**Solution**:

Since the circuit itself must self generate the next number in the sequence, the design must be able to hold the first two starting numbers in the sequence using 2 registers, and they should be reset respectively to 0 and 1.

Below is the block level diagram which contains two registers to hold the current number and the next number in the sequence. There is also control logic for the enable signal which when asserted, the output of the two flops are added together and then the result is stored in the next number register (on that same cycle the next number register shifts into the current number register). When the enable signal is low, the registers hold their previous value.

Below is the Verilog code:

Digital Logic RTL & Verilog Interview Questions |