Write Verilog code to design a digital circuit that generates the Fibonacci series

   I was interviewing with one company in Austin, TX and I was asked to design a circuit which would generate the Fibonacci Series.  By definition, the Fibonacci Series of numbers are 0, 1, 1, 2, 3, 5, 8, 13, etc.  By default, the first two numbers are 0, and 1 and the next number in the sequence is calculated by adding the previous two numbers.  The circuit also needed to support an enable input signal,  which would control if the circuit should advance and calculate the next number in the sequence , or hold its previous value.   

Solution:

   Since the circuit itself must self generate the next number in the sequence, the design must be able to hold the first two starting numbers in the sequence using 2 registers, and they should be reset respectively to 0 and 1.

   Below is the block level diagram which contains two registers to hold the current number and the next number in the sequence.   There is also control logic for the enable signal which when asserted, the output of the two flops are added together and then the result is stored in the next number register (on that same cycle the next number register shifts into the current number register).   When the enable signal is low, the registers hold their previous value.

Below is the Verilog code:

   This was just one question of over 50 questions that are in the Digital Logic RTL & Verilog Interview Questions Book.   The book contains 41 figures and drawings, and 28 pratical Verilog code examples.

Digital Logic RTL & Verilog Interview Questions

 You can purchase the Paperback book on Amazon or purchase the PDF E-Book version directly from us on our purchase page.

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Write Verilog Code to generate Gray Code

   A simple and common interview question for digital designers is to write Verilog code to generate Gray Code.   I’ve seen two ways to accomplish this.  The first method is converting the binary counter to Gray Code using a case statement.   However, there is an easier method, a more general use method that you should be aware of also.

   For example, below is RTL code to convert a 3bit binary counter to a Gray Code counter:

   A 3-bit register binary counter is incremented by 1 each clock cycle.   A signal named “gray_output” decodes the binary counter and then generates the new gray code output. 

   The problem with this approach is that for a Nbit

counter you need to explicitly decode each state. A better, more generic solution using an XOR gate is presented below:

   This was just one question of over 50 questions that are in the Digital Logic RTL & Verilog Interview Questions Book.   The book contains 41figures and drawings, and 28 pratical Verilog code examples.

Digital Logic RTL & Verilog Interview Questions

 You can purchase the Paperback book on Amazon or purchase the PDF E-Book version directly from us on our purchase page.

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Draw digital logic gates, truth tables, and equivalent transistor level circuits

It is a very basic question to ask for the truth table for all of the common digital logic gates (nand, nor, and, or, inverter) since this should be fundamentally understood.   However, I have also been asked to draw the cmos level transistor equivalent.    If you have been out of college for awhile, then it is important to brush up on the circuits.   Below are the tables showing the information:

This was just one question of over 50 questions that are in the Digital Logic RTL & Verilog Interview Questions Book.   The book contains 41figures and drawings, and 28 pratical Verilog code examples.

Digital Logic RTL & Verilog Interview Questions

 You can purchase the Paperback book on Amazon or purchase the PDF E-Book version directly from us on our purchase page.

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Design a Half Adder, Full Adder, and Multi-bit Adder

    A half adder is a circuit that receives two 1-bit inputs and adds them together to generate a 1-bit result output and a 1-bit carry.  The basic building blocks (gates) of a half adder consist of an XOR gate and an AND gate.   The below truth table and Kmap shows you again how these gates were chosen.

 As usual, we always start the design process by creating a truth table, showing all possible input combinations and writing down the expected output states.

Truth Table for Half Adder (Fig 2)

After you create the truth table, draw the Kmap for each output as shown in Fig. 3:

Fig 3

Author’s Tip:   It is important to understand how these basic building blocks are used together just in case you are asked.   It is too easy as a RTL designer to just type in Verilog:  R  = A + B;    Now you will have better understanding of what’s happening during synthesis.

  
This was just one question of over 50 questions that are in the Digital Logic RTL & Verilog Interview Questions Book.   The book contains 41figures and drawings, and 28 pratical Verilog code examples.

Digital Logic RTL & Verilog Interview Questions

 You can purchase the Paperback book on Amazon or purchase the PDF E-Book version directly from us on our purchase page.

Read More